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RTL Hardware IP Protection Using Key-Based Control and Data Flow Obfuscation

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2 Author(s)
Chakraborty, R.S. ; Dept. of EECS, Case Western Reserve Univ., Cleveland, OH, USA ; Bhunia, S.

Recent trends of hardware intellectual property (IP) piracy and reverse engineering pose major business and security concerns to an IP-based system-on-chip (SoC) design flow. In this paper, we propose a Register Transfer Level (RTL) hardware IP protection technique based on low-overhead key-based obfuscation of control and data flow. The basic idea is to transform the RTL core into control and data flow graph (CDFG) and then integrate a well-obfuscated finite state machine (FSM) of special structure, referred as ¿Mode-Control FSM¿, into the CDFG in a manner that normal functional behavior is enabled only after application of a specific input sequence. We provide formal analysis of the effectiveness of the proposed approach and present a simple metric to quantify the level of obfuscation. We also present an integrated design flow that implements the proposed obfuscation at low computational overhead. Simulation results for two open-source IP cores show that high levels of security is achievable at nominal area and power overheads under delay constraint.

Published in:

VLSI Design, 2010. VLSID '10. 23rd International Conference on

Date of Conference:

3-7 Jan. 2010

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