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This paper describes a clock generator for a double-sampled switched capacitor (SC) filtering system. The circuit is based on a fast charge-pump phase-locked loop (PLL) system that multiplies an external reference clock signal by a factor of eight and also ensures a high precision and stability of two internal nonoverlapped clock phases up to 80 MHz. This allows the driving of double-sampled SC filters up to 160 MHz sampling rate. The PLL is a third-order system with a bandwidth of 100 kHz and a lock-in time of 15 μs. The output clock jitter is 170 ps r.m.s. The total power consumption at 160 MHz is 25 mW and the total chip area is about 1 mm2
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:31
,
Issue:
10
)
Date of Publication: Oct 1996
- Page(s):
- 1560 - 1564
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 5408652
- Digital Object Identifier :
- 10.1109/4.540069
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Oct 1996
- Sponsored by :
- IEEE Solid-State Circuits Society
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