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Low voltage low power CMOS four-quadrant analog multiplier for neural network applications

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2 Author(s)
Colli, G. ; SGS-Thomson Microelectron., Agrate Brianza, Italy ; Montecchi, F.

A new low power CMOS four quadrant analog multiplier based on the operation of MOS transistors in linear region is presented. The simulated performances prove that it is possible to achieve an high input to supply ratio without a considerable amount of biasing current. Unlike almost all other designs of four quadrant multiplier in literature, this circuit allows a very low power dissipation (6 μW for cell) using both low biasing current (4 μA) and a 1.5 V supply. These properties make this circuit very suitable for ANN applications as a precise weighting synapse and for low power analog signal processing for portable applications. The circuit achieves an high linearity (less than 40 dB of Vina/b=1.5 Vpp@200 kHz) and a small area occupied (94 μm×88 μm with bias section included)

Published in:

Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on  (Volume:1 )

Date of Conference:

12-15 May 1996