The possibilities and problems of using PLL-Σ/Δ architecture to construct a RF to digital direct conversion receiver is investigated by taking different kinds of noises into consideration. The contribution of each noise in the receiver is analyzed by deriving the output response of the receiver in the z-domain and performing time-domain simulation. Some preliminary results are given
Published in:
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
(Volume:1
)
Date of Conference: 12-15 May 1996