RF to digital direct conversion receiver using PLL-/spl Sigma///spl Delta/ architecture: possibilities and problems

The possibilities and problems of using PLL-/spl Sigma///spl Delta/ architecture to construct a RF to digital direct conversion receiver is investigated by taking different kinds of noises into consideration. The contribution of each noise in the receiver is analyzed by deriving the output response of the receiver in the z-domain and performing time-domain simulation. Some preliminary results are given.