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The use of chemical-mechanical polishing (CMP) during the integrated circuit (IC) fabrication process has allowed for the aggressive interconnect patterning that is necessary for modern microprocessor technology. However, as IC technology has moved into the deep submicron realm, nonidealities during polishing have begun to play a significant role in device yield and circuit performance. In order to accurately predict circuit performance, designers must consider the effects of CMP prior to fabrication. A physics-based model to predict feature-scale wear of devices during polishing is presented and integrated into a CAD framework to test the model on various IC layouts. The model is benchmarked against experimental data and shown to be qualitatively accurate in predicting surface topography evolution.