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Browse Conference Publications > SOC Conference, 2009. SOCC 20 ... Help

A configurable length, Fused Multiply-Add floating point unit for a VLIW processor

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3 Author(s)
Chouliaras, V.A. ; Dept. of Electron. & Electr. Eng., Loughborough Univ., Loughborough, UK ; Manolopoulos, K. ; Reisis, D.

The efficiency of fused multiply add units plays a key role in the processor's performance for a variety of applications. A design keeping the advantages of the FMA regarding the latency and the hardware utilization and also improving the result's accuracy in both normalized and denormalized numbers is the subject of this work. The FMA unit has configurable latency and it is integrated in a VLIW processor. The VLSI TSMC 0.13 implementation achieved an operating frequency of 232.6 MHz and a final post-routed area of 121900.478 um2.

Published in:
SOC Conference, 2009. SOCC 2009. IEEE International

Date of Conference: 9-11 Sept. 2009

Page(s):
93 - 96
E-ISBN :
978-1-4244-4941-5
Print ISBN:
978-1-4244-4940-8
INSPEC Accession Number:
11134603
Conference Location :
Belfast
Digital Object Identifier :
10.1109/SOCCON.2009.5398088
Product Type:
Conference Publications

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