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The success of 3D ICs requires novel EDA techniques. Among them, this paper focuses on 3D IC partitioning, especially at the architectural level to maximize its benefits. We first derive logical formulations for 3D IC partitioning problems and then transform the formulations into integer linear programs (ILPs). The ILPs can minimize the footprint and the usage of vertical interconnects simultaneously. Our results conducted on the GSRC benchmark show that our approach outperforms the extended multi-way partitioning method in the usage of vertical interconnects under the same footprint settings. More importantly, our approach is very flexible and can readily extend to the partitioning problems with variant objectives and constraints, and with different abstract levels, e.g., from the architectural level down to the physical level. This flexibility makes the ILP formulations superior alternatives to the 3D IC partitioning problems.