By Topic

A 65-nm CMOS ultra-low-power LC quadrature VCO

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Kin Keung Lee ; Department of Electrical and Information Technology, Lund University, Box 118, 221 00, Sweden ; Carl Bryant ; Markus Törmänen ; Henrik Sjöland

An ultra-low-power LC quadrature VCO (QVCO) is presented. It is designed in a single-poly seven-metal 65 nm CMOS process. To minimize power dissipation an inductor with a high LQ product of 188 nH at 2.4 GHz, and a self-resonant frequency (fo) of 3.8 GHz, was designed. According to SpectreRF simulations the power dissipation is below 250 ¿¿W at a 0.6V supply. At this supply the simulated tuning range and phase noise at 1 MHz offset are 10.4% (2.34-2.59 GHz) and -113.4 dBc/Hz respectively. The phase noise figure of merit (FoM) is better than 187 dB at all supply voltages of interest, which is competitive to other state-of-the-art QVCOs.

Published in:


Date of Conference:

16-17 Nov. 2009