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A configurable fixed-point multiplier for digital signal processing (DSP) applications is proposed in this paper. It is implemented in four pipeline stages. The proposed multiplier supports multiple-precision operations, including one 32Ã32, two 16Ã32, two 16Ã16 or four 8Ã8 signed/unsigned multiplication operations and 16-bit or 8-bit dot product/double dot product operations. It is modeled in VerilogHDL and synthesized in 0.13 Â¿m CMOS technology. The critical path delay of the proposed design is 1.69 ns.