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This paper presents low-power characteristics of adiabatic complementary pass-transistor logic (ACPL) using two-phase AC power supply. Adiabatic CPL circuits consist of pure NMOS transistors, use CPL blocks for evaluation and bootstrapped NMOS switches to eliminate non-adiabatic loss of output loads. It is more suitable for design of flip-flops and sequential circuits, as it uses fewer transistors than other adiabatic logic circuits such as CPAL. In this paper, adiabatic flip-flops (D and JK) are proposed and a practical sequential circuit (4-bit shift register) is realized with adiabatic CPL. These flip-flops and sequential circuits have been simulated in CADENCE design tool at 90 nm technology and simulation results show that the proposed adiabatic CPL D flip-flop achieve power savings of 81% with CPAL, 88% with 2N-2N2P logic and JK flip-flop achieve 13% to 68% with CPAL, 69% to 91% with 2N-2N2P logic for clock frequencies from 50 to 300 MHz.
TENCON 2009 - 2009 IEEE Region 10 Conference
Date of Conference: 23-26 Jan. 2009