FPGA implementation of a high speed VLSI architecture for CORDIC

Coordinate rotation digital computer (CORDIC) based digital signal processing has become an important tool in consumer, communications, biomedical, and industrial products, providing designers with significant impetus for porting algorithm into architecture. Unfolded implementations of CORDIC algorithm can achieve low latency for rotation and various functions such as division, multiplication, logarithmic and exponential functions. Since the programmable approaches continue to progress in providing cost effective and high performance solutions, this paper presents a low latency field programmable gate array implementation of an unfolded architecture for the implementation of rotational CORDIC algorithm. This type of computational device is highly suitable for the implementation of customized hardware in portable devices where large parallelism and low clock rate can be utilized to meet low power consumption requirement.