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In this work, different combinations of low power techniques like multi-voltage, multi-threshold and clock gating, are applied on a general design candidate, an 8 bit RISC machine, to arrive at the optimal design combination which consumes minimum power and delivers maximum performance. A new metric called criticality rank is introduced to assign the different modules of design the multiple supply voltages and multiple threshold voltages. This rank is devised based on how critical the modules are with respect to delay incurred and presence in critical timing paths. A total of 16 design combinations are synthesized, timing analyzed and power analyzed using standard ASIC design flow at 90 nm node to arrive at two optimal designs. To decide the final optimal design, physical layouts are created and back annotation with RC parasitics and interconnect delay is done. Post layout timing and power analyses show a 42.5% power reduction and 33.3% performance improvement using combination of multi-threshold and clock gating as final optimal design.