Transient current sensing based completion detection with event separation logic for high speed asynchronous pipelines

This paper proposes a novel power supply transient current sensing based completion detector for single rail asynchronous systems to achieve high throughput compared to systems using speculative delay. This paper also proposes a new event separator logic for separating data tokens, in situations where the current sensor is idle due to consecutively same inputs. This type of logic is indispensable for asynchronous systems that use current sensing for completion detection. In order to prove the efficacy of the proposed CSCD, an asynchronous 8-bit Add-Compare-Select unit (ACSU) is simulated through HSPICE in 0.18¿m CMOS process operating at 1V with the proposed CSCD with event separator over MOUSETRAP and also with matched delay over MOUSETRAP. The throughput of the proposed CSCD is 2.2Gsps which is 37.5% higher than that of the matched delay whose throughput is 1.6Gsps.