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Field-programmable gate arrays (FPGA) are drawing increasing interest because of its performance, power consumption and configurability. They execute wide range of parallelizable algorithms which changes in accordance to variations in wireless channel statistics are utilized in smart antenna array embedded systems. In this article, we've described the FPGA implementation of a QRD processor that enables the run-time definition of the input matrix dimensions. The design employs a mixture of CORDIC-based processing (array boundary cell) and MAC based (array internal cell) arithmetic that is well matched to the computational resources of an FPGA like the Xilinx Virtex-2 Pro. We have made a projection of resource estimation for the processor when implemented as a whole array and as an embedded system with a micro processor and reduced number of internal and boundary cells.