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In this paper, a design flow for the design of calibrated pipeline analog-to-digital converters (ADCs), and a framework for their behavioral modeling is presented. The model includes also second order effects such as nonlinearities and linear and nonlinear memory errors, thus allowing fast and accurate simulations of the ADC behavior. In this way, background calibration techniques can be simulated during the design phase, allowing the optimization of ADC performance even under process variations. The design flow can be used to extract information about sensitivity to operating and environmental conditions, post-calibration performance and also design yield, by extracting a database of Monte Carlo realizations of the ADC stages, so that it can be employed to optimize system and circuit design. Simulations using a 0.13-μm CMOS technology show an accuracy of the model as high as 17 bits.