By Topic

Behavioral Modeling for Calibration of Pipeline Analog-To-Digital Converters

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Centurelli, F. ; Dipt. di Ing. Elettron., Univ. di Roma La Sapienza, Rome, Italy ; Monsurrò€, P. ; Trifiletti, A.

In this paper, a design flow for the design of calibrated pipeline analog-to-digital converters (ADCs), and a framework for their behavioral modeling is presented. The model includes also second order effects such as nonlinearities and linear and nonlinear memory errors, thus allowing fast and accurate simulations of the ADC behavior. In this way, background calibration techniques can be simulated during the design phase, allowing the optimization of ADC performance even under process variations. The design flow can be used to extract information about sensitivity to operating and environmental conditions, post-calibration performance and also design yield, by extracting a database of Monte Carlo realizations of the ADC stages, so that it can be employed to optimize system and circuit design. Simulations using a 0.13-μm CMOS technology show an accuracy of the model as high as 17 bits.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:57 ,  Issue: 6 )