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High Speed High Throughput FFT/IFFT Processor ASIC for Mobile Wi-Max

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1 Author(s)
Taral D. Chhatbar ; Electron. Eng. Dept., S.V. Nat. Inst. of Technol., Surat, India

This paper represents high speed and high throughput pipelined Fast Fourier Transform and its inverse (FFT/IFFT) for Mobile Wi-MAX. Modified architecture also provides concept of local ROM module and variable length support from 128~2048 point for FFT/IFFT. UMC 0.18 ¿m is used to design the same. FFT/IFFT chip consumes 266.81 mW at 40 MHz, 130.74 mW at 20 MHz and 65 mW at 10 MHz for length of 2048 point. Its core size is 2.6 mm × 2.6 mm with 51.25 ¿s execution time. Its latency is 2050 clock cycle with maximum clock frequency 40 MHz. Start up time for the chip is N/2 clock cycle where N is the length of FFT/IFFT. 16 bit word length with fixed point precision is used for entire implementation. As Wi-MAX is used for Metropolitan Area Network, it uses Orthogonal Frequency Division Multiple Access scheme. Speed of data transfer in Wi-MAX demands high throughput and high latency FFT/IFFT processor.

Published in:

2009 Second International Conference on Emerging Trends in Engineering & Technology

Date of Conference:

16-18 Dec. 2009