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Exploiting Parallelism through High Level Optimization on a Heterogeneous Multicore SoC

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4 Author(s)
Ming Yan ; Sch. of Comput., Nat. Univ. of Defense Technol., Changsha, China ; Peng Zhao ; Ziyu Yang ; Sikun Li

This paper describes a heterogeneous multicore SoC named EVMP-SoC, which is composed of a RISC host processor and two minor-different SIMD synergistic processor that are specially optimized for embedded visual media applications. By using on chip memory and the multi-channel memory access unit, this chip achieved several different level of parallelism, such as single-instructionstream-multiple-datastream (SIMD) data-level parallelism (DLP), multicore thread-level parallelism (TLP) and memory tile pipeline parallelism. We used an affine transformation framework called PLuTo on code optimization for EVMPSoC and explored multiple level parallelism on this chip. We found that lacking of processor performance model, the general polyhedral affine transformation framework could not generate efficient parallel code for heterogeneous architectures. Tile scheduling and pipelining techniques are adopted to make a full use of process cores and memory bandwidth. The experiment results showed that tile schedule and pipeline is effective. This chip gained a very good accelerate ratio after all the parallel optimizations. Finally, the chip was proved to be high efficiency and availability through a case study (a typical application of three dimensional reconstruction from multi images).

Published in:

Parallel and Distributed Systems (ICPADS), 2009 15th International Conference on

Date of Conference:

8-11 Dec. 2009