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FPGA-based low-complexity high-throughput tri-mode decoder for quasi-cyclic LDPC codes

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4 Author(s)
Xiaoheng Chen ; Dept. of Electr. & Comput. Engineeringis, Univ. of California, Davis, CA, USA ; Qin Huang ; Shu Lin ; Akella, V.

This paper presents an FPGA-based implementation of a tri-mode decoder for decoding the cyclic (4095,3367) Euclidean geometry LDPC code which has minimum distance 65 and no trapping set of size less than 65. The implementation integrates three compatible decoding algorithms in a single decoder. The three decoding algorithms are the one-step majority-logic decoding (OS-MLGD) algorithm and two iterative binary message passing algorithms (IBMP) derived from the OS-MLGD algorithm, one based on soft reliability information and the other on hard reliability information. All three algorithms requires only binary logical operations, integer additions, and single-bit messages, which makes them significantly less complex in terms of hardware requirements than sum-product algorithm, with a very modest loss in performance. The implementation is based on the partially parallel architecture and is optimized to take advantage of the high-speed dual-ported block RAMs in a Xilinx Virtex-4 FPGA. An optimization called memory sharing is introduced to take advantage of the configurable data width (word size) of the block RAMs to accommodate the 262080 edges in the Tanner graph of the (4095,3367) code. A technique is introduced to decode two codewords simultaneously to take advantage of the depth of the block RAMs. As a result, the proposed implementation achieves a throughput of 1.9 Gbps on a Virtex-4 LX160 FPGA and supports bit-error rate simulation down to 10-11 in a day or so.

Published in:

Communication, Control, and Computing, 2009. Allerton 2009. 47th Annual Allerton Conference on

Date of Conference:

Sept. 30 2009-Oct. 2 2009