A pseudo-pipelined VLSI architecture of two elliptic curve scalar multiplications

Two elliptic curve scalar multiplications (ECMLT) are used in some important elliptic curve encryption algorithms, a pseudo-pipelined VLSI architecture of two ECMLTs over GF(2
^m
) is proposed for these algorithms. The proposed architecture includes three word-serial finite field (FF) multipliers, and each FF multiplier has word size w. Implemented using FPGA, two ECMLTs are computed in approximately 4¿m/w¿(m-1)clock cycles in the proposed architecture. Compared with the architectures proposed by other authors recently, it is shown that the computation time for two ECMLTs is the shortest by using our proposed architecture.