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VLSI design of signal processing algorithm involves multiple selections and trade-off in order to achieve performance that is required for a particular application. In the case of realizing adaptive channel equalizer, digital circuit designers are confronted with three main design criteria that significantly affect the outcome of the circuit; filter structure and architecture, adaptive algorithm, and arithmetic components. This paper reviews some of the design techniques and strategies to achieve high performance adaptive equalizer based on optimal trade-off between the criteria. In addition to this, ASIC design of adaptive equalizer targeted to TSMC 0.25 Â¿m process technology is also presented. Simulation results show that the designed VLSI adaptive equalizer can successfully equalize distorted signals with ISI, with core cell layout area and throughput of 0.562 mm2 and 223 Kb/s respectively, which is suitable for mobile communication applications.