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Efficient techniques for realizing large-size signed multipliers in FPGAs

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3 Author(s)
Shuli Gao ; Dept. of Electr. & Comput. Eng., R. Mil. Coll. of Canada, Kingston, ON, Canada ; Al-Khalili, D. ; Chabini, N.

This paper presents four approaches for realizing large-size signed multipliers using embedded multiplier blocks in FPGAs. These approaches include new sign-extension, segment based Baugh-Wooley, sign-magnitude-based, and multi-granular. The target platforms are Xilinx' and Altera's FPGAs. The implementation results are compared with the standard approach utilized by commercial tools. On average, a delay reduction of 21% is achieved by multi-granular approach, and area saving of about 69% in terms of number of ALUTs is obtained by the new sign-extension approach.

Published in:

Microelectronics, 2008. ICM 2008. International Conference on

Date of Conference:

14-17 Dec. 2008

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