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Digital delta-sigma modulators (DDSMs) usually belong to one of two classes called multi-stage noise shaping (MASH) DDSMs and single-quantizer (SQ) DDSMs. A reduced complexity (RC) MASH DDSM was proposed and its design methodology was presented. In this paper, we apply a similar design strategy to the SQ-DDSM. We show that the RC SQ-DDSM can achieve similar performance but with nearly 20% less hardware compared with the conventional SQ DDSM, when designed with our methodology.