The changing trend of user applications and operating system design objectives for parallel computing by reconfigurable FPGAs

High performance computing (HPC) by parallel computing effort faces several challenges. The first challenge is the efficient design and management of the parallel computing resources of the hardware platform. The second challenge is the transformation of the sequential program meant for classic Von Neumann architecture to explicit parallel instruction computing (EPIC) architecture. The third challenge is the design of an efficient operating system (OS) for task scheduling and mapping on hardware platform for higher resource utilization and load balancing. Though need for HPC and the development of parallel hardware platforms are evolving over the last three decades, the application developers are still not familiar with the parallel programming styles and of the exploration of the parallel resources of the hardware platform. This paper is a comprehensive analysis of the required hardware platform, required functionalities of an efficient OS and required mechanisms for changing the sequential program to parallel program for the HPC platform developed with multiple microprocessors and multiple hardware accelerators of FPGAs. This analysis is based on the currently available technologies which can enable HPC on the parallel computing platform.