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A 10-bit low-power SAR ADC with a tunable series attenuation capacitor

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2 Author(s)
Filipovic, L. ; Dept. of Electron., Carleton Univ., Ottawa, ON, Canada ; MacEachern, L.

A 10-bit successive approximation analog-to-digital converter (ADC), with offset correction circuitry and a tunable series attenuation capacitor is presented for implantable biosensor applications. The ADC is designed in a standard 0.13 ¿m CMOS process technology and can operate with supply voltages down to 0.6 V. The ADC uses MOSFETs that are designed to operate in the sub-threshold region of operation. The ADC achieved sample rates of up to 500 kS/s with all 1024 codes present and an INL and DNL of 0.1009LSB and 0.1429LSB respectively. A power dissipation of 20.9 pJ/cycle was measured, while operating at 100 kS/s, with a 0.6 V supply voltage and an INL and DNL of 0.2585LSB and 0.2862LSB respectively, with all codes present. With a 1.0 V VDD, a 320 kS/s signal achieved an INL and DNL of 0.1623LSB and 0.2858LSB, respectively, with all codes present. A series attenuation capacitor is used to reduce the size of the circuit. Since processing variations can change the value of this capacitor and degrade the ADC operation, it was designed to vary between 401.7 fF to 487.5 fF using five digital input bits. Without process variations, the optimal variable capacitor code was designed to be the middle code, ¿10000¿.

Published in:

Microelectronics, 2008. ICM 2008. International Conference on

Date of Conference:

14-17 Dec. 2008