By Topic

The Impact of Oxide Traps Induced by SOI Thickness on Reliability of Fully Silicide Metal-Gate Strained SOI MOSFET

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Cheng-Li Lin ; Dept. of Electron. Eng., Feng Chia Univ., Taichung, Taiwan ; Yu-Ting Chen ; Fon-Shan Huang ; Wen-Kuan Yeh
more authors

In this letter, we investigate the effects of oxide traps induced by various silicon-on-insulator (SOI) thicknesses (T SOI) on the performance and reliability of a strained SOI MOSFET with SiN-capped contact etch stop layer (CESL). Compared to the thicker T SOI device, the thinner T SOI device with high-strain CESL possesses a higher interface trap (N it) density, leading to degradation in the device performance. On the other hand, however, the thicker T SOI device reveals inferior gate oxide reliability. From low-frequency noise analysis, we found that thicker T SOI has a higher bulk oxide trap (N BOT) density, which is induced by larger strain in the gate oxide film and is mainly responsible for the inferior TDDB reliability. Presumably, the gate oxide film is bended up and down for the p- and nMOSFETs, respectively, by the net stress in thicker T SOI devices in this strain technology.

Published in:

Electron Device Letters, IEEE  (Volume:31 ,  Issue: 2 )