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A CMOS power amplifier (PA) for a UHF (860-960 MHz) stationary RFID reader is presented. To design a high power and power efficient CMOS PA, quasi four pair structure and integrated passive device (IPD) transformers are used. An amplitude modulation is performed through the cascode gate with a pulse shaping filter. The chips are fabricated in a 0.18 ??m CMOS process and IPD. Measurements show output power of 32.8-33.37 dBm and the power added efficiency (PAE) of 51.8-56.1% with the supply voltage 3.0 V.
Date of Publication: Feb. 2010