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An Experimental 50-Megacycle Arithmetic Unit

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4 Author(s)

An experimental 50-megacycle arithmetic unit has been built which performs a repetitive multiplication program and checks the results for errors. The unit uses pulse circuitry which has been developed to perform digital operations at a 50-megacycle pulse-repetition rate. This paper describes the arithmetic system and the circuits which perform the required functions. These circuits include a full binary adder, a phase-locked frequency divider which provides a 3.125-megacycle secondary timing source, a reshaping and retiming circuit using germanium diodes and capacitive storage, a high-speed shift register, a high-speed indicator register, and a binary word generator.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:1 ,  Issue: 3 )

Date of Publication:

July 1957

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