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A Circuit Packaging Model for High-Speed Computer Technology

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4 Author(s)

An exploratory model has been constructed in a study of packaging and circuit techniques for a high-speed computer technology. An Arithmetic and Logic Unit capable of processing 64-bit words in floating-point format was fully designed. From this design a nucleus system comprising 424 circuits and 1838 transistors was abstracted, built, and tested. In this model, a delay of 2.2 nsec per level of logic was achieved in worst-case paths. This figure includes the wiring and power driver delays.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:7 ,  Issue: 3 )

Date of Publication:

July 1963

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