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An exploratory model has been constructed in a study of packaging and circuit techniques for a high-speed computer technology. An Arithmetic and Logic Unit capable of processing 64-bit words in floating-point format was fully designed. From this design a nucleus system comprising 424 circuits and 1838 transistors was abstracted, built, and tested. In this model, a delay of 2.2 nsec per level of logic was achieved in worst-case paths. This figure includes the wiring and power driver delays.
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