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Pert as an Aid to Logic Design

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2 Author(s)

A new application is presented for pert, the well-known statistical project-scheduling method. Using PERT, the logic designer could circumvent usually unrealistic worst-case criteria. He substitutes a formalized statistical method which determines (1) expected or most probable delays, (2) critical timing paths, (3) timing slack allowable between various inputs, and (4) probability of achieving an output by a certain time. From these data the designer can make a meaningful judgment regarding the reliability of his system. Significantly, he may achieve high reliability without being forced to resort to worst-case design.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

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IBM Journal of Research and Development  (Volume:10 ,  Issue: 2 )