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Parametric Study of Temperature Profiles in Chips Joined by Controlled Collapse Techniques

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1 Author(s)
Sevgin Oktay ; IBM Components Division laboratory, Poughkeepsie, New York 12602, USA

Parameters governing the temperature profiles of typical semiconductor chips joined to circuit module substrates by controlled chip collapse (flip-chip bonding) techniques are discussed. These include the physical and geometric properties of various layers of metals and non-metals that form the chip-to-substrate interconnection. The importance of the bond between the interconnection and the substrate from the point of view of interfacial thermal resistance is indicated. Also, the “thermal pinch” effects of voids in controlled chip collapse interconnections are discussed. The various thermal impedances as obtained from computer simulated temperature profiles are given graphically as functions of the parameters. The derivation of a semi-empirical expression for predicting the transient response of junctions on joined chips is shown.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:13 ,  Issue: 3 )