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System Validation by Three-level Modeling Synthesis

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3 Author(s)
Duke, K.A. ; Systems Development Division at the laboratory in Poughkeepsie, New York, USA ; Schnurmann, H.D. ; Wilson, T.I.

The experimental three-level system modeling technique discussed in this paper can be used during the design stage of a system for identifying mismatches among the architectural, microprogramming, and hardware logic levels. Compatible switching between modeling levels is emphasized. Execution of an application program by the architectural and microprogramming level models with switching between levels is illustrated.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:15 ,  Issue: 2 )