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Ge Epitaxial Refill Deposition Techniques for Fabricating Pedestal Transistor Structures

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4 Author(s)
Silvestri, V.J. ; IBM Thomas J. Watson Research Center, Yorktown Heights, New York 10598, USA ; Light, T.B. ; Yu, H.N. ; Reisman, A.

An etch-epitaxial refill technique is described for the fabrication of integrated high-speed Ge transistor structures having a pedestal configuration. The device areas surrounding 0.1 ohm-cm mesa structures were refilled with Ge having a resistivity range of 1 to 10 ohm-cm, providing low parasitic capacitance in the passive area of the base-collector junction. Processes and techniques were developed for minimizing the ridge that tends to form at the edge of the deposited SiO2 mask. Electrical properties and junction characteristics of the epitaxial regions are discussed and some device results presented.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:16 ,  Issue: 1 )