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Performance of Very High Density Charge Coupled Devices

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1 Author(s)
Patrin, N.A. ; IBM System Products Division Burlington Laboratory, Essex Junction, Vermont 05452, USA

The results of an experimental study of the performance of very high density 8, 128, and 256 bit CCD shift register structures are presented. The primary topics discussed include transfer efficiency, frequency response, impact of “fat zero” operation, and observed temperature dependency.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:17 ,  Issue: 3 )

Date of Publication:

May 1973

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