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Array Logic Macros

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1 Author(s)
J. W. Jones ; IBM United Kingdom Laboratories, Hursley, Winchester, Hampshire, England, UK

A macro design approach is discussed which combines the cost-effective attributes of array logic structures with those of random logic. These macros utilize the following features: (a) internal feedback registers for performing sequential logic, (b) masking and submasking to reduce the number of words in the array for certain functions, (c) control of the array's output level to vary the apparent size of the array, (d) decoding on input pairs and/or exclusive oring on output pairs for increasing the number of logic levels, and (e) random-access memory in the feedback and its use in interrupt handling. The macros are explained by specific design examples. This paper also discusses standard logic circuits in combination with an array structure to produce a component that can be used efficiently in specific data processing areas. The designer may elect to define an array logic macro which is a combination of some of the features given in this paper. The guideline for this selection is based upon the features necessary in an array structure to be competitive with a random logic LSI chip.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:19 ,  Issue: 2 )