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Analysis of the Merged Charge Memory (MCM) Cell

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1 Author(s)
Lee, H.S. ; IBM System Products Division laboratory, Essex Junction, Vermont 05452, USA

This paper describes a new MOS dynamic RAM (Random-Access Memory) cell which utilizes a merged surface charge transistor structure. The merged charge memory (MCM) cell uses a polysilicon electrode as both a bit sense line and common plate for a column of storage capacitors. The MCM structure is self-aligned, contactless and free of closely spaced p-n junctions. Its spatial density approaches the conceptual limit of the intersection formed by two orthogonal lines or 4W2 where W is the minimum geometry feature. The cell area utilization efficiency is improved because of this simplicity. Preliminary experimental results and ASTAP simulations based on the charge control equivalent circuit for a dynamic potential well are described. Implications for chip design constraints are discussed, and the advantages and limitations of MCM are highlighted where appropriate.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:21 ,  Issue: 5 )