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Design of Large ALUs Using Multiple PLA Macros

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1 Author(s)
Schmookler, Martin S. ; IBM General Systems Division laboratory, 11400 Burnett Road, Austin, Texas 78758, USA

This paper describes methods of designing large Arithmetic and Logical Units (ALUs) using multiple Programmable Logic Array (PLA) macros in which the outputs are obtained in one cycle corresponding to one pass through any PLA. The design is based on the well-known technique of providing conditional sums and group carries in parallel and selecting the proper sum using gating circuits. The PLA for each group of bits uses an adder design published by Weinberger in which each bit of the sum is formed from the EXCLUSIVE-OR of two outputs of the OR array. By placing the gating circuits in front of the EXCLUSIVE-OR circuits, the sums can be obtained using two OR array outputs for each bit and one additional OR array output for each internal string of bits. Also discussed are how ALUs containing more than two groups can obtain the group carries using a separate carry-look-ahead PLA macro and how this macro can be compressed by using special decoders and special physical design layout techniques. Additionally, the paper demonstrates how the PLAs can be used to provide detection of overflow and of zero results, and to also provide Boolean operations.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:24 ,  Issue: 1 )