By Topic

A Charge Injection Transistor Memory Cell

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Ho, I.T. ; IBM Data Systems Division laboratory, East Fishkill, New York, USA ; Riseman, J. ; Greenhaus, H.

In this paper, two versions of an experimental bipolar dynamic memory cell are described. The memory cell consists of one p-channel MOSFET and a bipolar npn transistor with extensive node sharing. The MOSFET device controls the charge injection into the floating base of the npn transistor, and the bipolar device provides amplification for the stored charge during read operation. For memories, this cell offers performance associated with bipolar technology and chip density comparable to MOSFET memories.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:24 ,  Issue: 3 )