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Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product

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3 Author(s)
Stapper, C.H. ; IBM General Technology Division laboratory, Essex Junction, Vermont 05452, USA ; McLaren, A.N. ; Dreckmann, M.

A model with mixed Poisson statistics has been developed for calculating the yield for memory chips with redundant lines and for partially good product. The mixing process requires two parameters which are readily obtained from product data. The product is described in the model by critical areas which depend on the circuit's sensitivity to defects, and they can be determined in a systematic way. The process is represented in the model by defect densities and gross yield losses. These are measured with defect monitors independently of product type. This paper shows how the yield for any product can be calculated given the critical areas, defect density, and mixing parameter. Future yields are forecast by using expected improvements in defect densities. Examples show good agreement between actual and calculated yields.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:24 ,  Issue: 3 )