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1/N Circuit and Device Technology

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6 Author(s)
Bhattacharyya, A. ; IBM Thomas J. Watson Research Center, Yorktown Heights, New York 10598, USA ; Gaffney, D.P. ; Kenyon, R.A. ; Mollier, P.B.
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The 1/N memory cell is the bipolar analog of the FET one-device cell. A thin dielectric and doped polysilicon are combined with bipolar technology to achieve a vertically integrated, high-density, fast-performance memory chip. The circuit design, device structure, and processing implementation for a 64K-bit dynamic, 1/N fractional-device, experimental bipolar memory are presented. Test results for several geometrical and structural variations, including 16K-bit storage arrays, are given.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:24 ,  Issue: 3 )