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Reduction of Leakage by Implantation Gettering in VLSI Circuits

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2 Author(s)
Geipel, H.J. ; IBM General Technology Division laboratory, Essex Junction, Vermont 05452, USA ; Tice, W.K.

Damage introduced by ion implantation on the back side of the wafer is used to reduce the MOS transient (relaxation) and junction leakage; the technique is applied to dynamic memory cells. Conditions necessary to ensure efficient gettering by various species (B, Ar, Kr, and Xe) are established based on achieving a sufficient density of b = ½ 〈110〉 dislocations. When the implantation occurs through a screen oxide, dose levels of less than 3 × 1014 ions/cm2 for Ar were found to be suitable. Equivalent leakage reduction was obtained for all species. Specifically, B at 5 × 1015 ions/cm2 was as effective in reducing relaxation leakage as was 1 × 1015 ions/cm2 of Ar for the particular thermal history of the investigated process.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:24 ,  Issue: 3 )