Skip to Main Content
Ever-increasing density poses significant challenges to the device designer, who must relate an integrated technology to the numerous electrical characteristics required for successful memory design. Success of a VLSI technology depends as much on the extensive design of small devices as on the sophisticated lithography with which to fabricate them. Several dimensional limitations arise from the electrical characteristics both of intentionally switching devices and of possible parasitic devices. Account must be taken of threshold dependence on both channel length and width. Furthermore, any isolation scheme must not introduce leakage from the storage node, such as parasitic subthreshold and low-level punch-through currents. Hot electron emission depends on both horizontal and vertical dimensions and must be minimized to guarantee the requisite long-term device behavior. This paper will briefly discuss the physical origins of the above fundamental device phenomena, their influence on SAMOS device design, and implications for future memory technologies.
Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.