By Topic

Circuit Implementation of Fusible Redundant Addresses on RAMs for Productivity Enhancement

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $33
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
B. F. Fitzgerald ; IBM General Technology Division laboratory, Essex Junction, Vermont 05452, USA ; E. P. Thoma

This paper describes the circuit schemes used to substitute redundant storage locations for defective ones found during testing. Word or bit lines are added along with appropriate bit steering circuitry to allow the replacement of a defective word or bit line. On-chip storage elements are “set” by the tester and used to store the binary addresses of the failing word or bit lines, which are then compared to the incoming addresses by the redundancy circuitry. This circuitry then activates the replacement word or bit lines and, by various means described, steers out the defective ones. A variation is described briefly which includes a word redundant circuit scheme that provides no penalty in memory access time by using separate sense amplifiers for the redundant lines.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:24 ,  Issue: 3 )