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Design of 2.5-Micrometer Josephson Current Injection Logic (CIL)

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1 Author(s)
Gheewala, T.R. ; IBM Thomas J. Watson Research Center, Yorktown Heights, New York 10598, USA

This paper describes Josephson Current Injection Logic (CIL) circuits. The design of the basic logic circuits, the two-and four-input OR and AND gates, and a timed inverter circuit, is presented in full detail and the logic delay and its sensitivity to design and fabrication parameters are investigated using detailed models of devices based on a 2.5-µm technology. The nominal logic delay of the circuits is estimated at 36 ps per gate for an average fan-in of 4.5 and fan-out of 3. The corresponding average power dissipation is 3.4 microwatts per gate. Finally, experimental delay measurements are presented for two-input and four-input OR and AND gates. The delay experiments are in excellent agreement with computer simulations.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:24 ,  Issue: 2 )

Date of Publication:

March 1980

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