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In integrated circuits, components are frequently interconnected by horizontal and vertical wires in respective wiring planes whether on chip, card, or board. The wire changes direction through “vias” that connect the orthogonal wiring planes. Because of technology constraints, the arrangement of vias must conform with certain neighborhood restrictions. We present results on the guaranteed minimum number and maximum possible number of vias in a given wiring cell for various technology constraints. These numbers provide an early means of control on global wiring routes to further the success of the exact embedding process that follows global wiring.
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