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Number of Vias: A Control Parameter for Global Wiring of High-Density Chips

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3 Author(s)
Lee, D.T. ; Northwestern University, Evanston, Illinois 60201, USA ; Hong, S.J. ; Wong, C.K.

In integrated circuits, components are frequently interconnected by horizontal and vertical wires in respective wiring planes whether on chip, card, or board. The wire changes direction through “vias” that connect the orthogonal wiring planes. Because of technology constraints, the arrangement of vias must conform with certain neighborhood restrictions. We present results on the guaranteed minimum number and maximum possible number of vias in a given wiring cell for various technology constraints. These numbers provide an early means of control on global wiring routes to further the success of the exact embedding process that follows global wiring.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:25 ,  Issue: 4 )

Date of Publication:

July 1981

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