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A High-Density Bipolar Logic Masterslice for Small Systems

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4 Author(s)
Chen, J.Z. ; IBM General Technology Division laboratory, East Fishkill Facility, Hopewell Junction, New York 12533, USA ; Chin, W.B. ; Jen, T.-S. ; Hutt, J.

A new high-density bipolar logic masterslice which uses a simple Schottky Transistor Logic (STL) circuit cell as its basic building block is presented in this paper. The STL cell is derived from Integrated Injection Logic (I2L). The use of low-barrier Schottky diodes for AND logic, as diodes function in Diode Transistor Logic (DTL), makes possible achieving the NAND circuit operation. A brief description of the Schottky diode fabrication process is also given. A new concept of contact hole personalization is introduced and is shown to be an efficient approach to masterslice design as well as a factor in achieving high cell density. Due to the unusual structure of the basic cell and the arrangement of the cells in the masterslice, a new physical design methodology was developed for the design of different part numbers, corresponding to unique logic functions, on this masterslice. The STL circuit operates with a 1.7-V power supply and yields a typical delay of 3 ns at 0.5 mW and 5 ns at 0.15 mW. The I/O circuits are TTL-level compatible. The cells, the circuits, the unique features of the masterslice, and its application in an I/O controller chip are described.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:25 ,  Issue: 3 )