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A 1024-Byte ECL Random Access Memory Using a Complementary Transistor Switch (CTS) Cell

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5 Author(s)
J. A. Dorler ; IBM General Technology Division laboratory, East Fishkill Facility, Hopewell Junction, New York 12533, USA ; J. M. Mosley ; G. A. Ritter ; R. O. Seeger
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This paper presents the design of a 1K-byte random access memory using a cross-coupled complementary transistor switch (CTS) cell. The memory operates with a 4.25-V power supply and achieves a 15-ns access time with a power dissipation of 1.8 W. This paper also demonstrates the advantages of using the CTS cell to achieve high circuit density and good performance of memory arrays. Array attributes, cell selection criteria, and cell operation (both ideal and in situ) as well as design considerations are covered. Hardware performance is also briefly summarized.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:25 ,  Issue: 3 )