Cart (Loading....) | Create Account
Close category search window
 

Exploiting instruction level parallelism with the DS architecture

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Yinong Zhang ; Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA ; Adam, G.B., III

A new architecture, DS, for exploiting instruction level parallelism is proposed in this paper. DS splits the program into two instruction substreams with the dominant one navigating the control flow and the subsidiary one carrying out the rest of the computational task. Compiler techniques associated with the DS architecture are discussed, with the goal of minimizing communication and balancing computation. Performance is compared with an aggressive 8-way superscalar processor. In general, DS can deliver the same IPC as the superscalar. This is achieved with less complex hardware and better potential for fast clock rates

Published in:

Parallel Processing, 1996. Vol.3. Software., Proceedings of the 1996 International Conference on  (Volume:1 )

Date of Conference:

12-16 Aug 1996

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.