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Bipolar Chip Design for a VLSI Microprocessor

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2 Author(s)
K. F. Mathews ; IBM General Technology Division laboratory, East Fishkill Facility, Hopewell Junction, New York 12533, USA ; L. P. Lee

In this paper, a pseudo-custom approach to bipolar VLSI chip design is presented, and a hierarchical structure of logic macros assembled from building blocks is described. A strategy of placing the logic macros along with algorithmically designed PLA structures and ROS with a placement aid, and of wiring the placement with an automatic wiring program, is discussed. The paper also focuses on the implementation of this strategy in terms of technology, chip structure, and chip design methodology. In addition, chip statistics are presented and their implications are discussed.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:26 ,  Issue: 4 )