By Topic

Physical Design of a Custom 16-Bit Microprocessor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Correale, Anthony ; IBM System Products Division laboratory, Neighborhood Road, Kingston, New York 12401, USA

The physical chip design aspects of a 16-bit, single-chip, custom-macro-designed microprocessor are described. This microprocessor represents the IBM System Products Division's highest-density VLSI FET processor design to date. The chip is a complex arrangement of over 6500 VLSI circuits utilizing a state-of-the-art polysilicon-gate HMOS-1 (high-performance MOS) technology. The physical design of this chip required the use of a comprehensive methodology, from conception through completion. The methodology used in the design of the microprocessor was based on a hierarchical approach and is presented in this paper.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:26 ,  Issue: 4 )