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Microprocessor Implementation of Mainframe Processors by Means of Architecture Partitioning

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2 Author(s)
Agnew, P.W. ; IBM System Products Division''s Advanced Systems Department, located at the Endicott laboratory, P.O. Box 6, Endicott, New York 13760, USA ; Kellerman, A.S.

The benefits of Large-Scale Integration (LSI) implementations have applied quite naturally to processors with relatively low performances and simple architectures; e.g., the one-chip microprocessors used in personal computers contain several thousand logic gates. Mainframe processors, however, have so far been limited to using logic chips that contain several hundred logic gates. The best use of LSI logic employs microprocessors to keep critical paths on chip, thus keeping pin counts and power dissipations within reasonable limits. Microprocessors have been extensively used to implement peripheral functions, such as I/O device control. However, as of this writing, a single state-of-the-art microprocessor cannot contain a mainframe processor function. Therefore, new machine organizations are needed to use today's state-of-the-art microprocessors to implement a mainframe processor. This paper examines several methods for applying LSI and microprocessors to the design of processors of increasing performance and complexity, and describes a number of specific approaches to microprocessor-based LSI implementation of System/370 processors. The most successful approaches partition the System/370 instruction set into subsets, each of which can be implemented by microcode on a special microprocessor or by programs written for an off-the-shelf microprocessor.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:26 ,  Issue: 4 )